Part A
74HC126D
Toshiba Halbleiter und Speicher
- Lifecycle
- Active
- Stock
- 7257 Stückzahl
- Package
- SOIC-14
- Series
- Logic c Puffer, Treiber, Empfänger, Transceiver
Replacement verdict
Compatible functional replacement candidate
The 74HC125D and 74HC126D are functionally compatible quad bus buffer gates with identical logic, package, and supply characteristics; the primary distinction lies in output enable polarity, which requires careful attention to control signal logic in the target design.
Logic Function
High match
Package Type
High match
Supply Voltage Range
High match
Output Enable Polarity
Validation required
Parts at a glance
Part B
74HC125D
Toshiba Halbleiter und Speicher
- Lifecycle
- Active
- Stock
- 3803 Stückzahl
- Package
- SOIC-14
- Series
- Logic c Puffer, Treiber, Empfänger, Transceiver
Key differences
Rows are prioritized by design impact. Highlighted values require attention during substitution.
Key electrical and mechanical differences between the two devices
| Parameter | 74HC125D | 74HC126D | Why it matters |
|---|---|---|---|
| Output Enable Logic | Active LOW (OE̅) | Active HIGH (OE) | Determines the control polarity required to enable each buffer's output; a direct swap changes when the output is driven versus high-impedance. |
| Number of Buffers | 4 | 4 | Defines how many independent channels are available in a single package for bus or signal buffering. |
| Output Type | 3-state (tri-state) | 3-state (tri-state) | Allows outputs to be placed in high-impedance state for shared bus connections without contention. |
| Supply Voltage Range | 2.0 V to 6.0 V | 2.0 V to 6.0 V | Specifies the compatible operating voltage window for the logic family and system rails. |
| Logic Family | HC (High-speed CMOS) | HC (High-speed CMOS) | Ensures comparable speed, drive strength, and CMOS input thresholds for drop-in electrical compatibility. |
| Propagation Delay (typical) | ~11 ns at 4.5 V | ~11 ns at 4.5 V | Affects timing margins in synchronous or high-speed signal paths. |
| Output Drive Current | ±6 mA at 4.5 V | ±6 mA at 4.5 V | Determines the load-driving capability for connected inputs, traces, or peripheral devices. |
| Package | SO14 (SOIC-14) | SO14 (SOIC-14) | Confirms physical footprint and pinout compatibility for PCB layout and assembly. |
| Operating Temperature Range | -40 °C to +125 °C | -40 °C to +125 °C | Ensures both parts meet the same environmental and reliability requirements for industrial or automotive use. |
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Full specification comparison
Use manufacturer datasheets as the final authority.
| Specification | 74HC126D | 74HC125D |
|---|---|---|
| Series | 74HC | 74HC |
| Part Status | Active | Active |
| Logic Type | Buffer, Non-Inverting | Buffer, Non-Inverting |
| Number of Elements | 4 | 4 |
| Number of Bits per Element | 1 | 1 |
| Output Type | 3-State | 3-State |
| Current - Output High Low | 7.8mA, 7.8mA | 7.8mA, 7.8mA |
| Voltage - Supply | 2V ~ 6V | 2V ~ 6V |
| Operating Temperature | -40°C ~ 125°C (TA) | -40°C ~ 125°C (TA) |
| Mounting Type | Surface Mount | Surface Mount |
Frequently asked questions
What is the main functional difference between the 74HC125D and 74HC126D?
The 74HC125D contains four independent non-inverting buffers with 3-state outputs that are enabled when the output enable (OE) input is LOW. The 74HC126D contains four independent non-inverting buffers with 3-state outputs that are enabled when the OE input is HIGH. Both are otherwise electrically similar quad bus buffer gates.
Are the 74HC125D and 74HC126D pin-compatible?
Yes. Both devices are offered in the same SOIC-14 package with identical pinouts: pins 1, 4, 10, and 13 are the OE inputs; pins 2, 5, 9, and 12 are the A inputs; pins 3, 6, 8, and 11 are the Y outputs; pin 7 is GND; and pin 14 is VCC. The only difference is the active logic level of the OE pins.
Can the 74HC125D and 74HC126D be used interchangeably in a design?
Not directly without logic-level consideration. Because the 74HC125D OE is active-LOW and the 74HC126D OE is active-HIGH, substituting one for the other requires inverting the enable signal or verifying that the driving logic polarity matches the required active level. Pinout and package compatibility alone do not guarantee functional equivalence.
What are the recommended operating conditions for the 74HC125D and 74HC126D?
Both devices typically operate from a supply voltage (VCC) of 2.0 V to 6.0 V over the -40 °C to +125 °C ambient temperature range, consistent with the 74HC family. Inputs are CMOS-compatible with high-impedance characteristics. Designers should consult the specific manufacturer datasheet for exact limits, as parameters may vary slightly between vendors.
What is the difference in propagation delay between the 74HC125D and 74HC126D?
There is no inherent propagation delay difference between the two devices. Both use the same non-inverting buffer architecture; the only distinction is the polarity of the output enable control. Propagation delay (tPD) is typically in the range of 8 ns to 15 ns at 4.5 V VCC, depending on load and manufacturer, and is essentially identical for both parts.
What is the output drive capability of the 74HC125D and 74HC126D?
Both devices typically provide standard 74HC output drive of ±4 mA at 4.5 V VCC and ±5.2 mA at 6.0 V VCC, sufficient for driving CMOS inputs and light bus loads. They are not intended as high-current line drivers. Verify the exact IOH/IOL ratings in the manufacturer datasheet for the specific part number and package.
When should I choose the 74HC125D over the 74HC126D?
Choose the 74HC125D when the enable signal is active-LOW, such as when a microcontroller or decoder output is LOW to enable the buffer. Choose the 74HC126D when the enable signal is active-HIGH. Selecting the correct polarity eliminates the need for an external inverter and reduces component count and propagation delay.
Do the 74HC125D and 74HC126D have the same 3-state output behavior?
Yes. Both devices place their outputs in a high-impedance state when disabled, allowing direct connection to a shared bus without contention. The only difference is the logic level required on the OE pin to enter or exit the high-impedance state: LOW enables the 74HC125D, while HIGH enables the 74HC126D.