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74AVC2T245GUX
+StücklisteIC TRNSLTR BIDIRECTIONAL 10XQFN
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HerstellerNexperia USA Inc.
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Herstellerteil #74AVC2T245GUX
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Datenblatt 74AVC2T245GUX DataSheet
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Paket XFQFN-10
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Auf Lager3163
365 Tage Qualitätsgarantie
7*24 Stunden-Servicegarantie
90-Tage Kundendienstgarantie
Originalproduktgarantie
Spezifikationen
| Attribut | Wert |
| Supplier | Nexperia USA Inc. |
| Package / Case | Tape & Reel (TR),Cut Tape (CT) |
| Series | 74AVC |
| Part Status | Active |
| Translator Type | Voltage Level |
| Channel Type | Bidirectional |
| Number of Circuits | 1 |
| Channelsper Circuit | 2 |
| Voltage - VCCA | 0.8 V ~ 3.6 V |
| Voltage - VCCB | 0.8 V ~ 3.6 V |
| Output Type | Tri-State, Non-Inverted |
| Data Rate | 500Mbps |
| Operating Temperature | -40°C ~ 85°C (TA) |
| Mounting Type | Surface Mount |
Übersicht
Description
Equivalent
- MC74AVC2T245 (Onsemi)
- 74AVC2T245 (Nexperia)
Note: packaging and lead-frame variants differ (GUX is TI’s package). Use a distributor cross-reference (Digi-Key/Mouser) to confirm exact package, voltage range, and availability.
Features
- Dual 4‑bit bidirectional bus transceivers (8 I/O total)
- Non‑inverting data paths
- 3‑state outputs with individual output‑enable control
- Separate direction control per 4‑bit block (A↔B data direction)
- A‑port and B‑port for flexible two‑way data transfer
- Wide operating voltage: Vcc in 2.5 V–5.5 V range; CMOS/TTL‑compatible input thresholds
- High‑speed CMOS performance with low power consumption
- Ioff (partial‑power‑down) support to prevent back‑powering
- ESD protection and RoHS‑compliant (GUX) packaging
Applications: bidirectional bus buffering and level/reset bridging between different voltage domains.
Pinout
- Function: Dual 2-bit bidirectional bus transceiver/voltage-level translator. Transfers data between A-side (VCCA) and B-side (VCCB) with DIR controlling direction and OE enabling tri‑state outputs. Used for level shifting and buffering between two voltage domains.
Manufacturer
Application
- Bidirectional four-bit bus buffering for microcontrollers/FPGA/ASIC data paths
- Level shifting between voltage domains (e.g., 3.3 V and 5 V) with tri-state I/Os
- Bus isolation and buffering on backplanes, motherboards, and connectors
- I/O expansion and rapid prototyping in digital systems
- Interface between processors and memories/peripherals using two independent 4-bit channels
- General high-speed data path buffering where controlled direction and tri-state behavior are needed.