Abbildungen dienen nur als Referenz
SI5345A-D04313-GMR
+StücklisteIC JITTER ATTENUATOR/MULTIPLEXER
-
HerstellerSkyworks Solutions Inc.
-
Herstellerteil #SI5345A-D04313-GMR
-
Datenblatt SI5345A-D04313-GMR DataSheet
-
Paket QFN-64
-
Auf Lager6667
365 Tage Qualitätsgarantie
7*24 Stunden-Servicegarantie
90-Tage Kundendienstgarantie
Originalproduktgarantie
Spezifikationen
| Attribut | Wert |
| Package / Case | Tape & Reel (TR) |
| Part Status | Active |
Übersicht
Description
Features
- Flexible jitter-cleaning clock generator with multi-output distribution
- Any-Output, Any-Frequency capability for programmable output clocks
- Internal PLLs/VCO-based frequency synthesis for precise, low-jitter clocks
- I2C (two-wire) control interface for programming frequencies, enables, and drive settings
- Programmable output enables/power-downs and glitch-free frequency switching
- Output clock monitoring and fault detection (loss of signal, out-of-lock indicators)
- Spread-spectrum clocking support to reduce EMI
- Suitable for high-speed SERDES, memory, PCIe, Ethernet, and other timing-critical sources
- RoHS-compliant packaging (GMR) with suitable footprint for dense designs
Note: The D04313-GMR suffix and package code denote lot/date and packaging, not functional differences.
Pinout
- Function: Multi-output clock generator / jitter-cleaning zero-delay buffer (programmable via I2C to synthesize multiple clock outputs from a reference).
Manufacturer
- What kind of company: A fabless semiconductor company that designs and sells mixed-signal ICs, including timing devices (clock generators/zero-delay buffers) and related embedded solutions.
Application
- High‑speed serial interfaces: PCIe, SATA/SAS, USB 3.x, HDMI/DisplayPort
- Networking/telecom equipment: switches, routers, line cards, PHY timing
- Data‑center/servers: CPU/memory/SoC clocks, PCIe and memory clock distribution
- FPGA/ASIC designs needing multiple synchronized clocks and SERDES references
- Consumer electronics and multimedia: video/audio timing
- Test and measurement gear requiring ultra‑low jitter reference clocks