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SN74AHC573PWR
+StücklisteIC OCT TRNSP D-TYP LATCH 20TSSOP
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HerstellerTexas Instruments
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Herstellerteil #SN74AHC573PWR
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Datenblatt SN74AHC573PWR DataSheet
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Auf Lager8398
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Spezifikationen
| Attribut | Wert |
| Supplier | Texas Instruments,Rochester Electronics, LLC |
| Package | Tape & Reel (TR),Cut Tape (CT),Bulk |
| Series | 74AHC |
| ProductStatus | Active |
| LogicType | D-Type Transparent Latch |
| Circuit | 8:8 |
| OutputType | Tri-State |
| Voltage-Supply | 2V ~ 5.5V |
| IndependentCircuits | 1 |
| DelayTime-Propagation | 1ns |
| Current-OutputHighLow | 8mA, 8mA |
| OperatingTemperature | -40°C ~ 85°C |
| MountingType | Surface Mount |
| Package/Case | 20-TSSOP (0.173, 4.40mm Width) |
Übersicht
Description
- D0–D7 data inputs and Q0–Q7 outputs
- LE (latch enable) and OE (output enable, active low)
- When LE = 1, Q follows D (data transparent)
- When LE = 0, Q holds the last latched value
- When OE = 0, outputs are enabled; when OE = 1, all outputs go Hi-Z
- Operates from 2.0 V to 5.5 V (CMOS levels), with low power and fast CMOS operation
- Used for buffering, data/address multiplexing, and temporary data storage in digital systems
- Packaging: RoHS-compliant lead-free package (PWR suffix), available in common 20-pin small packages
In short, it’s a versatile 8-bit latch/buffer ideal for latching and isolating bus data with controllable tri-state outputs.
Equivalent
- MC74AHC573 (ON Semiconductor)
- 74AHC573 (Nexperia)
- uPD74AHC573 (Renesas)
- μPD74AHC573 (ROHM)
Note: verify voltage range (typically 2–5.5 V), package, and pinout for a valid cross-reference.
Features
- 8-bit D-type transparent latch with 3-state outputs (Q0–Q7).
- LE (latch enable) input controls when D is latched; Q follows D while LE is asserted.
- OE (output enable) input provides tri-state outputs (high-impedance when not enabled).
- Wide supply range: Vcc = 2.0 V to 5.5 V; CMOS-compatible logic levels.
- High-speed Advanced CMOS (AHC) performance with low power consumption.
- Robust I/O: ESD protection and latch-up immunity.
- Packaging: PowerPAD-style (PWR) package for improved thermal performance.
- Flexible bus interfacing for microprocessor/microcontroller data/address buses and other latch/buffer needs.
Pinout
- Function: 8‑bit D-type transparent latch with 3‑state outputs. D0–D7 are data inputs; Q0–Q7 are tri‑state outputs. A latch‑enable input captures the D inputs, and an output‑enable input controls the tri‑state outputs.
Manufacturer
- Company type: American multinational corporation that designs and manufactures semiconductors and integrated circuits (analog, digital, and mixed-signal ICs).
Application
- Demultiplexing multiplexed address/data buses (ALE) in microprocessor/microcontroller systems.
- Data buffering between fast CPUs/FPGA/ASICs and slower peripherals, with tri-state enable for bus sharing.
- Glue logic and I/O expansion in embedded designs.
- Timing control, synchronization, and simple register storage in digital circuits.
- Display or graphics/data latching in video/graphics pipelines or peripheral controllers.